Among conventional non-volatile memories, a memory developed by Saifun Semiconductors Ltd. is a typical one. See Japanese Publication for Unexamined Patent Publication 2001-156189 (Tokukai 2001-156189; published on Jun. 8, 2001), an equivalent to U.S. Pat. No. 6,348,711 B1 (date of patent: Feb. 19, 2002). The following discusses the structure of this conventional memory and how erase operation is performed.
The memory, as shown in FIG. 8, includes a gate electrode 909, a first N-type diffusion layer region 902, and a second N-type diffusion layer region 903. The gate electrode 909 is provided above a P-well region 901 with an intervening gate insulating film. The first N-type diffusion layer region 902 and the second N-type diffusion layer region 903 are provided on a surface of the P-well region 901.
The gate insulating film is an “ONO” (Oxide Nitride Oxide) film, in which a silicon nitride film 906 is sandwiched between silicon oxide films 904 and 905. In the silicon nitride film 906, provided in the vicinity of respective ends of the first N-type diffusion layer region 902 and the second N-type diffusion layer region 903 are a first memory (charge) storage section 907 and a second memory (charge) storage section. Amounts of charge in the memory storage sections 907 and 908 can be independently read out in the form of drain currents of the transistor.
Discussed next is a method for erasing information from the memory. Here, to “erase” means to decrease electrons stored in the memory storage sections 907 and 908. In the erase operation disclosed in Japanese Publication for Unexamined Patent Publication 2001-156189, the electrons stored in the second memory storage section 908 are decreased by applying a positive voltage Vd to the drain electrode (the second N-type diffusion layer region 903), and a negative voltage Vg to the gate electrode 909.
When the voltages are applied, a PN junction between the P-well region 901 and the N-type diffusion layer region 903 is subjected to a strong reverse bias. The strong reverse bias causes inter-band tunneling, thereby generating holes. The holes are pulled toward the gate electrode, which is subjected to a negative voltage. Thus, the holes are injected into the second memory storage section 908. In the second memory storage section 908, the holes are bonded again with the electrons stored therein. As a result, the electrons stored in the second memory storage section 908 are virtually decreased. Information is thus erased from a specified one of the two memory storage sections 907 and 908.
However, it requires a high voltage to pull the electrons out of the memory storage section and lead the electrons toward the drain electrode. The conventional memory is problematic in this respect.
For example, as is clear from above, in order to erase information from the second memory storage section 908, it is necessary to cause the inter-band (band to band) tunneling at the PN junction between the P-well region 901 and the second N-type diffusion layer region 903. To cause the inter-band tunneling, the potential needs to show a sufficiently steep transition at the PN junction. This means that the PN junction needs to be subjected to a strong reverse bias. Thus, it requires a high voltage to rewrite information stored in a memory cell of the conventional memory.